- ROS 2 Hardware Acceleration Architecture and Conventions - REP-2008, version 2
- Integrating the Nav2 Stack with NVIDIA Isaac ROS GEMs
- In shift to new era, Wave Computing adopts RISC-V chip architecture
- What are CUDA Cores?
- Increasing Performance With Data Acceleration
- Intel FPGA used to hook non-x86 processors to Optane PMem
- The Road to Robotics: Where's the Industry Headed?
- Israel Innovation Authority’s Consortium of Robotics: Developing Next-Gen Human-Robot Interaction Capabilities
- ROS 2 Simplifies Hardware Acceleration for Robots
ROS 2 Hardware Acceleration Architecture and Conventions - REP-2008, version 2
Source: Hardware Acceleration in Robotics, April 18, 2022 
This article describes the architectural pillars and conventions required to introduce hardware acceleration in ROS 2 in a scalable and technology-agnostic manner. The content is inspired by the lastest draft of REP-2008 which is available at the REP-2008 Pull Request. In particular, this update includes improvements and the addition of a fourth pillar, cloud extensions, which allow bringing the hardware acceleration capabilities introduced in ROS 2 graphs also directly to the cloud.
Integrating the Nav2 Stack with NVIDIA Isaac ROS GEMs
Source: NVIDIA Technical Blog, April 19, 2022 
NVIDIA Isaac ROS GEMs are ROS packages that optimize AI-based robotics applications to run on NVIDIA GPUs and the Jetson platform. This work is done entirely in simulation and can be used as a starting point for transferring robotic capabilities from simulation to the real world (Sim2Real).
In shift to new era, Wave Computing adopts RISC-V chip architecture
Source: Reuters, April 19, 2022 
Silicon Valley's Wave Computing launching designs for two new microprocessors this year. RISC-V architecture is an open-standard instruction set architecture (ISA) and emerging rival to proprietary architecture from Britain's Arm, semiconductor technology firm owned by SoftBank Group Corp.
What are CUDA Cores?
Source: Trusted Reviews, April 19, 2022 
CUDA, which stands for Compute Unified Device Architecture, Cores are the Nvidia GPU equivalent of CPU cores that have been designed to take on multiple calculations at the same time, which is significant when you’re playing a graphically demanding game.
Increasing Performance With Data Acceleration
Source: Semiconductor Engineering, April 14, 2022 
In-line accelerator cards are becoming increasingly important in the data processing industry. Increasing demand for functions that require high acceleration per unit of data is providing a foothold for accelerators. The big questions are how to best approach this problem, and whether new technology will displace or replace existing solutions.
Intel FPGA used to hook non-x86 processors to Optane PMem
Source: Blocks and Files, April 19, 2022 
SMART Modular’s Kestral Optane Memory card connects to non-x86 processors with an Intel Stratix FPGA, which contains Optane controller functions.
The Road to Robotics: Where's the Industry Headed?
Source: Supply Chain News, April 13, 2022 
In the future of the robotics industry, Barkay envisions the “commoditization of hardware.” In keeping with the development trend of technology in other industries, he says, “Ultimately, software prevails.”
Israel Innovation Authority’s Consortium of Robotics: Developing Next-Gen Human-Robot Interaction Capabilities
Source: Korea IT Times, April 15, 2022 
This consortium will change the perception of robots in social situations, ushering in a new era of robotics. Developing these verbal and gesture languages within ROS will have an easy integration using Nimbus for future businesses to rapidly utilize in their next-gen robots.
ROS 2 Simplifies Hardware Acceleration for Robots
Source: Robotics Business Review, September 28 , 2021 
The process of creating optimized, hardware specific, compute architectures can be time consuming and complex. The ROS 2 Hardware Acceleration Working Group (HAWG) is working to simplify hardware acceleration engineering tasks by creating acceleration kernels based on open standards.
Customizable FPGA-Based Hardware Accelerator for Standard Convolution Processes Empowered with Quantization Applied to LiDAR Data
Source: MDPI, March 11, 2022 
In recent years there has been an increase in the number of research and developments in deep learning solutions for object detection applied to driverless vehicles. This application benefited from the growing trend felt in innovative perception solutions, such as LiDAR sensors. Currently, this is the preferred device to accomplish those tasks in autonomous vehicles. There is a broad variety of research works on models based on point clouds, standing out for being efficient and robust in their intended tasks, but they are also characterized by requiring point cloud processing times greater than the minimum required, given the risky nature of the application. This research work aims to provide a design and implementation of a hardware IP optimized for computing convolutions, rectified linear unit (ReLU), padding, and max pooling. This engine was designed to enable the configuration of features such as varying the size of the feature map, filter size, stride, number of inputs, number of filters, and the number of hardware resources required for a specific convolution. Performance results show that by resorting to parallelism and quantization approach, the proposed solution could reduce the amount of logical FPGA resources by 40 to 50%, enhancing the processing time by 50% while maintaining the deep learning operation accuracy.
A Survey of Network-Based Hardware Accelerators
Source: MDPI, March 25, 2022 
Many practical data-processing algorithms fail to execute efficiently on general-purpose CPUs (Central Processing Units) due to the sequential matter of their operations and memory bandwidth limitations. To achieve desired performance levels, reconfigurable (FPGA (Field-Programmable Gate Array)-based) hardware accelerators are frequently explored that permit the processing units’ architectures to be better adapted to the specific problem/algorithm requirements. In particular, network-based data-processing algorithms are very well suited to implementation in reconfigurable hardware because several data-independent operations can easily and naturally be executed in parallel over as many processing blocks as actually required and technically possible. GPUs (Graphics Processing Units) have also demonstrated good results in this area but they tend to use significantly more power than FPGA, which could be a limiting factor in embedded applications. Moreover, GPUs employ a Single Instruction, Multiple Threads (SIMT) execution model and are therefore optimized to SIMD (Single Instruction, Multiple Data) operations, while in FPGAs fully custom datapaths can be built, eliminating much of the control overhead. This review paper aims to analyze, compare, and discuss different approaches to implementing network-based hardware accelerators in FPGA and programmable SoC (Systems-on-Chip). The performed analysis and the derived recommendations would be useful to hardware designers of future network-based hardware accelerators.
Brain-inspired computing needs a master plan
Source: nature, April 13, 2022 
New computing technologies inspired by the brain promise fundamentally different ways to process information with extreme energy efficiency and the ability to handle the avalanche of unstructured and noisy data that we are generating at an ever-increasing rate. To realize this promise requires a brave and coordinated plan to bring together disparate research communities and to provide them with the funding, focus and support needed. We have done this in the past with digital technologies; we are in the process of doing it with quantum technologies; can we now do it for brain-inspired computing?
Hardware Acceleration in Robotics Newsletters
- Hardware Acceleration in Robotics #5 - Global robot software market to reach 7527 million $ in 2025, NVIDIA medical-grade chip with hardware acceleration and more
- Hardware Acceleration in Robotics #4 - Single-Chip Processors, a technical review of NVIDIA Jetson Orin and the new ROS 2 iRobot Create 3 and more
- Hardware Acceleration in Robotics #3 - Hardware-accelerated ROS 2 Pipelines, The Robotic Processing Unit (RPU) and more
- Hardware Acceleration in Robotics #2 - Nvidia Isaac ROS GEMs, Nvidia H100, updates to CUDA-X Libraries and more
- Hardware Acceleration in Robotics #1 - ROS2 for Self-Driving Cars, Intel world fastest FPGAs, Nvidia GTC and more
ROS 2 Hardware Acceleration Working Group meetings
- Hardware Acceleration WG, meeting #7
- Hardware Acceleration WG, meeting #6
- Hardware Acceleration WG, meeting #5
- Hardware Acceleration WG, meeting #4
- Hardware Acceleration WG, meeting #3
- Hardware Acceleration WG, meeting #2
- Hardware Acceleration WG, meeting #1
Mayoral, V. (2022, April 18). ROS 2 hardware acceleration architecture and conventions. Hardware Acceleration in Robotics. https://news.accelerationrobotics.com/ros-2-hardware-acceleration-architecture-and-conventions/ ↩︎
Bhide, A. (2022, April 19). Integrating the Nav2 stack with NVIDIA Isaac ROS GEMs. NVIDIA Technical Blog. https://developer.nvidia.com/blog/integrating-the-nav2-stack-with-nvidia-isaac-ros-gems/ ↩︎
Lee, J. L. (2022, April 19). In shift to new era, wave computing adopts RISC-V chip architecture. Reuters. https://www.reuters.com/technology/shift-new-era-wave-computing-adopts-risc-v-chip-architecture-2022-04-19/ ↩︎
Ryles, G. (2022, April 19). What are CUDA cores? Trusted Reviews. https://www.trustedreviews.com/explainer/what-are-cuda-cores-4226433 ↩︎
Degrasse, M. (2022, April 14). Increasing performance with data acceleration. Semiconductor Engineering. https://semiengineering.com/increasing-performance-with-data-acceleration/ ↩︎
Mellor, C. (2022, April 19). Intel FPGA used to hook non-x86 processors to Optane PMem. Blocks and Files. https://blocksandfiles.com/2022/04/19/intel-fpga-amd-arm-nvidia-optane-pmem/ ↩︎
Bowman, R. J. (2022, April 13). Watch: The road to robotics: Where's the industry headed? Supply Chain Brain - Supply Chain News, Analysis, Videos, Podcasts | SupplyChainBrain. https://www.supplychainbrain.com/articles/34864-watch-the-road-to-robotics-wheres-the-industry-headed ↩︎
Yeon, B. (2022, April 15). Israel innovation authority’s consortium of robotics: Developing Next-Gen human-robot interaction capabilities. Korea IT Times. https://www.koreaittimes.com/news/articleView.html?idxno=112354 ↩︎
Mayoral, V. (2021, September 28). ROS 2 simplifies hardware acceleration for robots. Robotics Business Review. https://www.roboticsbusinessreview.com/opinion/ros-2-simplifies-hardware-acceleration-for-robots/ ↩︎
Silva, J., Pereira, P., Machado, R., Névoa, R., Melo-Pinto, P., & Fernandes, D. (2022, March 11). Customizable FPGA-based hardware accelerator for standard convolution processes empowered with quantization applied to LiDAR data. MDPI. https://www.mdpi.com/1424-8220/22/6/2184/htm ↩︎
Skliarova, I. (2022, March 25). A survey of network-based hardware accelerators. MDPI. https://www.mdpi.com/2079-9292/11/7/1029/htm ↩︎
Mehonic, A., & Keynon, A. J. (2022, April 13). nature. https://www.nature.com/articles/s41586-021-04362-w ↩︎