- ROS 2 Hardware Acceleration Working Group - meeting #8
- Hardware Accelerating ROS 2 Nodes for Perception
- Implementing Real-Time, Multi-Camera Pipelines with NVIDIA Jetson
- Capitalizing on the Architectural Flexibility of FPGAs with RISC-V and a Simplified Programming Flow
- Arm Unveils New M85 Core and Expands IoT Virtual Hardware Offerings
- Innovative Interconnects: The Future of Chiplet-based Processors?
- Why RISC-V Is Succeeding
ROS 2 Hardware Acceleration Working Group
Source: ROS Discourse, April 27, 2022 
We discuss the group's progress during the last month showing how updates of REP-2008 to reflect cloud extensions, discuss ROS 2 perception Nodes performance using AMD KV260 and NVIDIA Jetson Nano and discuss how benchmarking results hint that FPGAs obtain 500x performance than GPUs.
The session also includes a guest talk provided by Jeffrey Ichnowski from the RISE lab and AUTOLAB at the University of California at Berkeley, which together with his team led “FogROS 2: An Adaptive and Extensible Platform for Cloud and Fog Robotics Using ROS 2”. This work led to ROS VSLAM (ORB-SLAM2) latency reductions of 50%, grasp planning optimizations going from 14s to 1.2s, and motion planning speedups of 28x.
Source: Hardware Acceleration in Robotics, April 26, 2022 
Robots moving faster require faster perception computations happening at the edge. This article discusses how hardware acceleration empowers faster robots and how it's important to select the right accelerator. Benchmarking results hint speedup differences of more than 500x between acceleration solutions for ROS Nodes.
Source: NVIDIA Technical Blog, April 21, 2022 
Multi-camera applications are essential for enabling autonomous robots, intelligent video analytics (IVA), and AR/VR. In this post,
Nvidia present jetmulticam, an easy-to-use Python package for creating multi-camera pipelines. Nvidia demonstrate a specific use case on a robot with a surround camera system.
Capitalizing on the Architectural Flexibility of FPGAs with RISC-V and a Simplified Programming Flow
Source: eetimes, April 26, 2022 
Efinix FPGAs offer a high-density device in a small package with low power consumption, and at a low price point. Using 16-nm process technology, they can pack in up to 1 million logic elements and integrated memory blocks in packages as small as 5.5 mm. Efinix's Quantum compute fabric has reconfigurable tiles, or exchangeable logic and routing (XLR) cells. This does away with traditional routing and allows LEs to be smaller and used more flexibly. Efinix FPGAs implement RISC-V CPU architectures without being bound to proprietary IP cores such as ARM.
Source: allaboutcircuits, April 26, 2022 
Six months after its Arm Total Solutions for IoT rollout, today Arm is growing the initiative with a new Cortex-M processor, expanded ecosystem tools, and new virtual hardware—all aimed at IoT.
Source: allaboutcircuits, April 18, 2022 
Many of the world's largest chipmakers like AMD, Intel, and NVIDIA are investing in chiplets. But heterogeneous processors are not without their flaws.
Source: Semiconductor Engineering, February 24, 2022 
RISC-V has enabled and promoted innovation. While free may be important to a segment of the industry, the real key is freedom. While additional hardware blocks may be open source, perhaps the most important gain will be the ability to quickly take an open specification for a processor and implement it.
Hardware Acceleration in Robotics Newsletters
- Hardware Acceleration in Robotics #6 - ROS 2 Hardware Acceleration Architecture including cloud, Nav2 integration with NVIDIA Isaac ROS GEMs, RISC-V chip adoption and more
- Hardware Acceleration in Robotics #5 - Global robot software market to reach 7527 million $ in 2025, NVIDIA medical-grade chip with hardware acceleration and more
- Hardware Acceleration in Robotics #4 - Single-Chip Processors, a technical review of NVIDIA Jetson Orin and the new ROS 2 iRobot Create 3 and more
- Hardware Acceleration in Robotics #3 - Hardware-accelerated ROS 2 Pipelines, The Robotic Processing Unit (RPU) and more
- Hardware Acceleration in Robotics #2 - Nvidia Isaac ROS GEMs, Nvidia H100, updates to CUDA-X Libraries and more
- Hardware Acceleration in Robotics #1 - ROS2 for Self-Driving Cars, Intel world fastest FPGAs, Nvidia GTC and more
ROS 2 Hardware Acceleration Working Group meetings
- Hardware Acceleration WG, meeting #7
- Hardware Acceleration WG, meeting #6
- Hardware Acceleration WG, meeting #5
- Hardware Acceleration WG, meeting #4
- Hardware Acceleration WG, meeting #3
- Hardware Acceleration WG, meeting #2
- Hardware Acceleration WG, meeting #1
Hardware Acceleration WG, meeting #8. https://discourse.ros.org/t/hardware-acceleration-wg-meeting-8/25147 ↩︎
Mayoral, V. (2022, April 26). Hardware accelerating ROS 2 nodes for perception. Hardware Acceleration in Robotics. https://news.accelerationrobotics.com/hardware-accelerating-ros-2-nodes/ ↩︎
Lewicki, T. (2022, April 21). Implementing real-time, multi-camera pipelines with NVIDIA Jetson. NVIDIA Technical Blog. https://developer.nvidia.com/blog/implementing-real-time-multi-camera-pipelines-with-nvidia-jetson/ ↩︎
Efinix. (2022, April 26). Capitalizing on the Architectural Flexibility of FPGAs with RISC-V and a Simplified Programming Flow. eetimes. https://www.eetimes.com/capitalizing-on-the-architectural-flexibility-of-fpgas-with-risc-v-and-a-simplified-programming-flow/ ↩︎
Child, J. (2022, April 26). Arm Unveils New M85 Core and Expands IoT Virtual Hardware Offerings. allaboutcircuits. https://www.allaboutcircuits.com/news/arm-unveils-new-m85-core-and-expands-iot-virtual-hardware-offerings/ ↩︎
Nijhawan, A. (2022, April 18). Innovative Interconnects: The Future of Chiplet-based Processors? allaboutcircuits. https://www.allaboutcircuits.com/news/innovative-interconnects-the-future-of-chiplet-based-processors/ ↩︎
BAILEY, B. (2022, February 24). Why RISC-V is succeeding. Semiconductor Engineering. https://semiengineering.com/why-risc-v-is-succeeding/ ↩︎