Hardware Acceleration in Robotics #6
Hardware acceleration in robotics news. ROS 2 Hardware Acceleration Architecture and conventions including cloud, Nav2 Stack integration with NVIDIA Isaac ROS GEMs, RISC-V adoption increases.
FPGA
Field Programmable Gate Arrays (FPGAs) are semiconductor devices that are based around a matrix of configurable logic blocks (CLBs) connected via programmable interconnects. After manufacture, FPGAs can be reprogrammed to meet specific functionality or application needs. This characteristic sets FPGAs apart from Application Specific Integrated Circuits (ASICs), which are made specifically for a given design goal.
Hardware Acceleration in Robotics #4
Hardware acceleration in robotics news. Updates about Single-Chip Processors, NVIDIA Jetson AGX Orin, iRobot Create 3 with ROS 2.
Hardware Acceleration in Robotics #3
Hardware acceleration in robotics news. Updates about hardware-accelerated ROS 2 Pipelines, Optimizers in SS-SAM and an interview with Rob Telson about a chip that mimicks the human brain.
Hardware accelerated ROS 2 pipelines and towards the Robotic Processing Unit (RPU)
We show how FPGAs compare to GPUs for ROS 2 graphs and propose the Robotic Processing Units (RPU), robot-specific processors that map ROS computational graphs efficiently to CPUs, FPGAs and GPUs to obtain best peformance.
Modern Robotics Compute Architectures
Robot behaviors are often built as computational graphs, with data flowing from sensors to compute technologies, all the way down to actuators and back. Roboticists must map these graph-like structures efficiently to computing platforms to obtain best performance.
ROS 2 Simplifies Hardware Acceleration for Robots
The process of creating optimized, hardware specific, compute architectures can be time consuming and complex. The ROS 2 Hardware Acceleration Working Group (HAWG) is working to simplify hardware acceleration engineering tasks by creating acceleration kernels based on open standards.
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