News

EFPGAs bring a 10X advantage in power and cost

Source: Semiconductor Engineering, July 11, 2022 [1]
Integrating FPGAs into the main SoC can reduce power and cost by as much as 10X. Integrating the FPGA can reduce costs from $300 down to $20 of additional silicon cost. The need for improved processing in the cloud is driven by faster search results.

Introducing QODA: the platform for hybrid quantum-classical computing

Source: NVIDIA Technical Blog, July 12, 2022 [2]
The past decade has seen quantum computing leap out of academic labs into the mainstream. Now is the time to build the tools needed to deliver valuable quantum applications. NVIDIA is announcing the launch of Quantum Optimized Device Architecture (QODA) for hybrid quantum-classical computing.

A new programming language for hardware accelerators

Source: Tech Xplore, July 11, 2022 [3]
MIT scientists have created a new programming language for writing high-performance code for hardware accelerators. Exo is built around a concept called "Exocompilation". Engineers can use Exo to turn a simple matrix multiplication into a more complex program, which runs orders of magnitude faster.

AMD expects GPUs to need 600W of power in 2025

Source: TweakTown, July 10, 2022 [4]
Next-gen AMD and NVIDIA graphics cards will use up to 600W of power. AMD has set a new goal of hitting 30x better energy efficiency by 2025. This is aimed at the machine learning, and high-performance computing (HPC) markets in data centers.

Now Comes The Hard Part, AMD: Software

Source: The Next Platform, July 8, 2022 [5]
AMD's acquisition of Xilinx was as much about software as it was about hardware. FPGAs are programmable gates, but that was not as important as access to new embedded customers. The combined company has over 6,000 customers and is on track to grow by 22 percent or so this year. Of that, $13 billion is from the datacenter market and $33 billion is embedded systems. Central to AMD's strategy is "pervasive AI," using a mix of CPUs, GPUs, and FPGAs.

RISC-V serves up open-source possibilities for the future

Source: Electronic Design, July 12, 2022 [6]
RISC-V offers a level of flexibility to design new processors because the instruction set isn’t defined at the ISA level, but rather is the compilation of the processor and other design parameters.

Advancing robotic assembly with a novel simulation approach using NVIDIA Isaac

Source: NVIDIA Technical Blog, July 11, 2022 [7]
Robotic assembly is essential across the automotive, aerospace, electronics, and medical industries. It is one of the oldest and most challenging tasks in robotics.

Chip paves the way for better self-driving vehicles and portable devices

Source: Innovation Origins, July 7, 2022 [8]
A study by the Politecnico di Milano has found a way to separate and distinguish optical beams even if they are superimposed. This operation is made possible by a programmable photonic processor built on a silicon chip of just 5 mm2, it says. A new photonic chip has been developed at the Politecnico di Milano in Italy. It allows information quantities of over 5000 GHz to be managed, 100 times greater than current high-capacity wireless systems.

Flex Logix working with Microsoft to build secure chips

Source: New Electronics, July 13, 2022 [9]
Flex Logix Technologies, a supplier of embedded FPGA (eFPGA) IP, architecture and software, has been selected to be part of a team of microelectronic companies, led by Microsoft, to build a chip development platform for security as demonstrated by the DoD RAMP Project.

DSP-based radar, LiDAR, comms processing optimizes auto apps

Source: Electronic Design, July 8, 2022 [10]
Built on Cadence’s Tensilica Xtensa customizable processor architecture, the ConnX DSPs implement systems at power levels that reduce the need for hardware accelerators.

Professor in ECE earns $175k NSF grant to optimize device performance

Source: Auburn University , June 29, 2022 [11]
Deep learning and artificial intelligence programs require large data sets that can inhibit desired levels of speed and accuracy. Mehdi Sadi's proposed solution will optimize performance and decrease power usage without increasing device size. He has been awarded a two-year, $174,923 grant from the National Science Foundation.

Designing arithmetic circuits with deep reinforcement learning

Source: NVIDIA Technical Blog, July 8, 2022 [12]
As Moore's law slows down, it becomes increasingly important to develop other techniques that improve the performance of a chip at the same technology process node. Our approach uses AI to design smaller, faster, and more efficient circuits for each chip generation. The latest NVIDIA Hopper GPU architecture has nearly 13,000 instances of AI-designed circuits.

Papers

YASMIN: yet another state machine library for ROS 2

Source: arXiv.org, May 27, 2022 [13]
YASMIN is a library specifically designed for ROS 2 for easing the design of robots using state machines. State machines are a common mechanism for defining behaviors in robots, defining them based on identifiable stages. It is available in C++ and Python and includes a web viewer for monitoring the execution of the system.

Resource-constrained FPGA implementation of YOLOv2

Source: SpringerLink, May 29, 2022 [14]
YOLOv2, an 8-bit deep CNN containing 50.6 MB weights, uses low-resource of 8.3 Mbits of on-chip memory and 4.8 W of low-power consumption. We present a resource-constrained Field-Programmable gate array implementation with optimized data transfer and computing efficiency.

Previous Hardware Acceleration in Robotics Newsletters

Past ROS 2 Hardware Acceleration Working Group meetings

  1. Jaros, A. (2022, July 11). EFPGAs bring a 10X advantage in power and cost. Semiconductor Engineering. https://semiengineering.com/efpgas-bring-a-10x-advantage-in-power-and-cost/?cmid=cdce4845-fc90-46de-bc02-eabdc2f7679f ↩︎

  2. McCaskey, A. (2022, July 12). Introducing QODA: The platform for hybrid quantum-classical computing. NVIDIA Technical Blog. https://developer.nvidia.com/blog/introducing-qoda-the-platform-for-hybrid-quantum-classical-computing/ ↩︎

  3. Gordon, R. (2022, July 11). A new programming language for hardware accelerators. Tech Xplore - Technology and Engineering news. https://techxplore.com/news/2022-07-language-hardware.html ↩︎

  4. Garrefa, A. (2022, July 10). AMD expects GPUs to need 600W of power in 2025. TweakTown. https://www.tweaktown.com/news/87281/amd-expects-gpus-to-need-600w-of-power-in-2025/index.html ↩︎

  5. Morgan, T. P. (2022, July 8). Now comes the hard part, AMD: Software. The Next Platform. https://www-nextplatform-com.cdn.ampproject.org/c/s/www.nextplatform.com/2022/07/08/now-comes-the-hard-part-amd-software/amp/ ↩︎

  6. Atwell, C. (2022, July 12). RISC-V serves up open-source possibilities for the future. Electronic Design. https://www.electronicdesign.com/technologies/embedded-revolution/article/21246374/electronic-design-riscv-serves-up-opensource-possibilities-for-the-future ↩︎

  7. Omotuyi, O. (2022, July 11). Advancing robotic assembly with a novel simulation approach using NVIDIA Isaac. NVIDIA Technical Blog. https://developer.nvidia.com/blog/advancing-robotic-assembly-with-a-novel-simulation-approach-using-nvidia-isaac/ ↩︎

  8. Chip paves the way for better self-driving vehicles and portable devices. (2022, July 7). Innovation Origins. https://innovationorigins.com/en/selected/chip-paves-the-way-for-better-self-driving-vehicles-and-portable-devices/ ↩︎

  9. Tyler, N. (2022, July 13). Flex Logix working with Microsoft to build secure chips. New Electronics. https://www.newelectronics.co.uk/content/news/flex-logix-working-with-microsoft-to-build-secure-chips ↩︎

  10. Slovick, M. (2022, July 8). DSP-based radar, LiDAR, Comms processing optimizes auto apps. Electronic Design. https://www.electronicdesign.com/markets/automotive/article/21246175/electronic-design-dspbased-radar-lidar-comms-processing-optimizes-auto-apps ↩︎

  11. McAdory, J. (2022, June 29). Professor in ECE earns $175k NSF grant to optimize device performance when using AI. Auburn University Samuel Ginn College of Engineering - in Alabama. https://www.eng.auburn.edu/news/2022/06/professor-in-ece-earns-nsf-award-to-optimize-computer-memory-bottlenecks.html ↩︎

  12. Roy, R., Raiman, J., & Godil, S. (2022, July 8). Designing arithmetic circuits with deep reinforcement learning. NVIDIA Technical Blog. https://developer.nvidia.com/blog/designing-arithmetic-circuits-with-deep-reinforcement-learning/ ↩︎

  13. González-Santamarta, M. A., Rodríguez-Lera, F. J., Fernández, C., Rico, F. M., & Matellán, V. (2022, May 27). YASMIN: Yet Another State MachINe library for ROS 2. arXiv.org . https://arxiv.org/pdf/2205.13284.pdf ↩︎

  14. Zhang, Z., Parvez, M. A., & Kouzani, A. Z. (2022, May 29). Resource-constrained FPGA implementation of YOLOv2. SpringerLink. https://link.springer.com/article/10.1007/s00521-022-07351-w ↩︎